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* Studienarbeit Christopher Odenbach *
* *
* WS98/99 *
* *
* mit Dank an Willi *
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* MOTOROLA MC68HC705X32 *
* *
* Initialising subroutine *
* *
* *
* *
* *
* *
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INIT EQU *
RSP ;reset stack pointer
JSR INIT_PROCESSOR
JSR INIT_CAN_IDENT
JSR INIT_MCAN_IF
JSR INIT_SCI_IF
JSR INIT_VARIABLES
WAITLOOP wait
BRA WAITLOOP
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* Initializing Processor
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INIT_PROCESSOR EQU *
RTS
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* Initializing CAN identifiers
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INIT_CAN_IDENT EQU *
LDA #$00
STA MASTER ;Master identifier 000 00000
LSLA ;shift 3 bits left
LSLA
LSLA
AND #$E0
STA SENDER_ID_1 ;left 3 bits of ID (SENDER_ID_1 = xxx00000)
LDA MASTER
AND #$03
LSLA ;shift 6 bits left
LSLA
LSLA
LSLA
LSLA
LSLA
STA SENDER_ID_2 ;right 2 bits of ID (SENDER_ID_2 = xx000000)
CLRA
STA SCI ;SCI identifier $00
LDA #$20
STA K_BUS ;K_BUS identifier $20
RTS
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* Initializing the MCAN interface
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INIT_MCAN_IF EQU *
LDA #$01 ; set RR Bit to access other registers
STA CCNTRL
LDA MASTER ;acceptance code = Master's ID (irrelevant)
STA CACC
LDA #$FF ;no bits should be compared
STA CACM
LDA #$01 ;SJW=1xTscl, P=2 ==> Tscl = 2*P/f_osc = 1 īs @ 4MHz
STA CBT0
LDA #$B4 ;Tseg1=5, Tseg2=4, three samples per bit
STA CBT1 ;==> Tbit=10 īs => 100 KBit/s
LDA #$DF ;TX1 Push-pull, TX0 Push-pull inv., CAN mode 2
STA COCNTRL
LDA #$22 ; clear RR bit => MCAN will operate normally
STA CCNTRL
LDA #$84 ;RX0 passive, release receive buffer
STA CCOM
RTS
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* Initializing the SCI interface
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INIT_SCI_IF EQU *
LDA #$02
STA SCCR1
LDA #$2E ;receiver int., transm., receiver, rec. wake up enable
STA SCCR2
LDA #$C0
STA BAUD ; NP=13, NT=1, NR=1 => 9.6 KBaud @ 4 MHz, Fosc/2
LDA #$10 ; default: Khepera with ID=10000 has SCI access via IR
STA SCI_ID
RTS
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* Initializing variables
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INIT_VARIABLES EQU *
CLRA
STA RAM
STA BC_IN
LDX #$08 ;clear the RAM transmit buffer
NXTBYTE CLRA
STA SCI_TX_RAM-1,X
DECX
BNE NXTBYTE
LDA #01
STA RX_RAM_ACC ;set the receive RAM buffer access
CLRA
STA RAM_SIZE
STA CNT3
STA ROBNR
LDA PORT_C
AND #$1F
STA MODE
CMP #$01
BEQ SAY_HELLO
BRA RETURN
SAY_HELLO JSR PRINT_RESET
RETURN RTS
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